1. Field of the Invention
The present invention relates to a time-divisional register for temporarily storing data to be used in respective time-divisional channels when time-divisional processing is performed and, more particularly, to a time-divisional data register used for asynchronously transferring data from a first apparatus (e.g., a CPU) to a second apparatus (e.g., a sound source of an electronic musical instrument) for performing time-divisional processing at a relatively long period.
2. Description of the Prior Art
In a digital electronic musical instrument, the operations of the overall apparatus are controlled using a central processing unit (CPU). In this case, the CPU fetches data from respective operation members such as a keyboard, a pedal, and the like, and forms musical tone control data for controlling synthesis of tones on the basis of these operation member data. The CPU then transfers the formed data to a sound source. In order to allow polyphonic tone generation without complicating a circuit arrangement as much as possible, the sound source performs time-divisional processing with which a memory, an arithmetic circuit, and the like can be shared by a plurality of channels.
FIG. 7 shows a conventional time-divisional data register for transferring data such as tone control data from the CPU to the sound source in the electronic musical instrument. FIG. 4B shows operation timings of the respective sections of the register. The sound source executes 16-channel time-divisional processing at a 1-25-.mu.s processing period T.sub.A for each channel, i.e., at a relatively long time-divisional period T.sub.D of 20 .mu.s for 16 channels, so as to allow polyphonic tone generation of 16 tones.
In FIG. 7, a 16-stage shift register 1 is driven in response to a clock CLKA, and sequentially shifts data supplied to an input terminal IN and those stored in the respective stages to an output side at the period T.sub.A. More specifically, data supplied to the input terminal IN is transmitted to an output terminal OUT with a delay of 16.times.T.sub.A (=T.sub.D).
In FIG. 4B, a clock CLKA is a clock having the period T.sub.A (1.25 .mu.s), and a clock CLKD is a clock having the period T.sub.D (=16.times.T.sub.A =20 .mu.s).
In FIG. 7, a selector 2 is normally applied with an L-level signal at its select terminal SA, selects data DTA supplied to an input terminal B, and supplies the selected data to the input terminal IN of the shift register 1. More specifically, data written in the shift register 1 is normally circulated at the time-divisional period T.sub.D, and tone forming data of corresponding channels are sequentially output in synchronism with the processing period T.sub.A of each time-divisional channel in the sound source.
When data DTA to be supplied to the sound source is to be rewritten, a CPU (not shown) supplies new data DATA, a number CH of a time-divisional channel whose data is to be rewritten with the new data, and an L-level write instruction signal R/W. The data DATA is supplied to a latch 3, the channel number CH is supplied to a channel timing coincidence detection circuit 4, and the write instruction signal R/W is supplied to an inverter 5. The write instruction signal R/W is set at L level since it designates a normal read mode at H level.
The latch 3 latches the data DATA in response to the leading edge of the clock CLKD. The channel timing coincidence detection circuit 4 comprises a channel counter (not shown) for counting the clock CLKA. When a channel number as a count value of the channel counter coincides with the channel number CH sent from the CPU, the circuit 4 outputs an H-level coincidence signal CT. FIG. 4B shows a case wherein the channel number CH designated by the CPU is 5.
The H-level coincidence signal CT is supplied to one input terminal of an AND gate 6. On the other hand, the other input terminal of the AND gate 6 receives an H-level signal obtained by inverting the L-level write instruction signal R/W by the inverter 5. Therefore, the output from the AND gate 6 goes to H level, and is supplied to the select terminal SA of the selector 2. Thus, the selector 2 selects the output data supplied from the latch 3 to its input terminal A, and supplies the selected data to the input terminal IN of the shift register 1. The respective stages of the shift register 1 fetch data at their input side in response to the leading edge of the clock CLKA. More specifically, data in first to 15th stages of the shift register 1 are shifted by one stage at a timing corresponding to the channel number CH (=5) designated by the CPU, and are stored in the second to 16th stages. At the same time, the data DATA latched by the latch 3 is written in the first stage of the shift register 1.
In this manner, in the conventional time-divisional data register, an access time for rewriting one data is equal to one time-divisional period T.sub.D (=20.mu.s). More specifically, an apparatus which transfers data (e.g., a CPU) cannot execute next write processing until a timing corresponding to a channel to which data to be transferred of an apparatus which receives data (e.g., a sound source) is reached, and the data write processing is ended. For this reason, the CPU may have to wait for a maximum of 2.times.T.sub.D =40 .mu.s until one data is written in a given channel. In particular, when a plurality of data are to be written, a long time is undesirably required for write processing.
When, e. g. , the CPU directly writes data in a plurality of channels without using the latch 3, if data are written in all the 16 channels, a total of a wait time until a timing corresponding to the first channel, and a write time requires a maximum of 2T.sub.D, and a long time is required for write processing again.
When a plurality of peripheral devices which perform time-divisional processing at different periods are connected, it is difficult to perform parallel data transfer between time peripheral devices and a first apparatus so as to shorten a processing time in the first apparatus.